The ever increasing complexity of today's integrated circuits presents new engineering problems in the field of test generation. Historically, test generation for integrated circuits occurred manually, and generally, at the end of the circuit design cycle. Consequently, the quality and fault coverage of the test program suffered. In order to address the numerous problems associated with testing more complex and sequential integrated circuit, scan-based design methodologies were developed. These scan-based design methodologies simplify the testing of complex circuits by partitioning the overall circuit into a collection of small, combinational logic blocks. Structured testing of the combinational logic systems, used to implement VLSI circuits, requires the use of test patterns (vectors) consisting of every possible input state for the combinational logic block under test. Typically, these test patterns are generated using some form of computer automated test pattern generation (ATPG) software. Accordingly, the optimum structured test methodology is one designed to facilitate its use with the ATPG software.
FIG. 1 illustrates a standard scan structure using a D-type scan Master-Slave flip-flop 10 (SDFF), for use with ATPG software. This SDFF 10 receives either a scan data input (SDI) or a normal data input (D), from scan input multiplexor 12, in response to the activation of the scan enable (SE) signal. For example, when the SE signal is a logic low, the normal data (D) input signal is scanned into a master latch 14, when the CLOCK signal is a logic low, and stored. When the CLOCK signal switches to a logic high, the D input is transferred to a slave latch 16. Conversely, when the SE signal is a logic high, the scan data input (SDI) signal is scanned into the master latch 14 (when the CLOCK signal is a logic low), and subsequently transferred to the slave latch 16, when the CLOCK signal switches to a logic high. Thus, the master latch 14 passes the input signal (D or SDI) when the CLOCK signal is a logic low, and the slave latch 16 receives and passes the input signal when the CLOCK signal switches to a logic high.
Typically, in a structured design, all storage elements in the design may be set to a specific logic value. Accordingly, using the structure shown in FIG. 1, a SDI value is scanned into the SDFF 10 when the scan enable (SE) signal is active, and "captured" when the SE signal is disabled. During the "capture" interval, the SDI value is presented to the actual logic (i.e. combinational logic block) for evaluation, and the resultant data value(s) scanned out for analysis. Proper operation of the D-type scan element requires that the input signal be stable for a few nanoseconds before the device is clocked (the set-up time), and the data must remain stable for a few nanoseconds after the clocking is initiated (hold-time). Thus, although the D-type scan element allows the use of ATPG programs, thereby reducing the time and manpower required for test generation, it requires more set-up time than other storage elements. Consequently, when designing structured logic, one of the issues is how to resolve the circuit problem of insufficient set-up time for a standard scan flip-flop.
In cases where structured design guidelines are not required, domino logic may be employed where necessary to allow for short set-up times and to provide high performance. Domino logic does not, however, fit within the current specifications for ATPG programs, therefore, the circuit designer must manually generate the test patterns for the domino logic portion of the circuitry. FIG. 2 illustrates a domino logic circuit 20 for implementing the function (A*B)+(C*D)+(B*D). The circuit comprises p-channel transistors 22 and 32, n-channel transistors 23,24,25,26,27,28,29,30, and 31, and an inverter 33. When the CLOCK signal is a logic low, transistor 22 precharges a node 34 to a logic high value. When the CLOCK signal switches to a logic high value, the domino logic function is evaluated. The input signals A,B, C, and D must be stable at all times during the interval of time in which the CLOCK signal is a logic one. If the input signals A, B, C, or D are unstable, charge sharing may occur, causing the precharged node 34 to be discharged. The discharging of the precharge node 34 causes the output (OUT) to toggle, and provide an erroneous output signal. This occurrence is typically referred to as a "hazard" problem. Generally, there is no recovery from the "hazard" problem during the current clock phase. Domino logic evaluates the function exceptionally fast, however, due to this "hazard" sensitivity, it generally does not fit within the current structured design guidelines or ATGP capabilities. The actual operation of the domino logic circuitry will be explained later.
Shown in FIG. 3 is a logic diagram of a circuit 40 for implementing the same function ((A*B)+(C*D)+(B*D)) incorporating scan path design. The circuit 40 comprises three AND gates 42,44 and 46, an OR-gate 48, and the scan data flip-flop (SDFF) 10 of FIG. 1. This scan circuit 40 captures the evaluation of the decode function at the rising edge of the CLOCK signal. Although scan circuit 40 eliminates the requirement that the inputs remain stable whenever the CLOCK is a logic one, it requires more set-up time than the domino logic circuit 20 of FIG. 2. Furthermore, implementation of circuit 40 requires more transistors than the domino logic circuit 20 (FIG. 2).